The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to post manufacturing analysis of semiconductor devices including analyzing and debugging circuitry within an integrated circuit.
Recent technological advances in the semiconductor industry have permitted dramatic increases in circuit density and complexity, and commensurate decreases in power consumption and package sizes for integrated circuit devices. Single-chip microprocessors now include many millions of transistors operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A byproduct of these technological advances has been an increased demand for semiconductor-based products, as well as increased demand for these products to be fast, reliable, and inexpensive. These and other demands have led to increased pressure to manufacture a large number of semiconductor devices at an efficient pace while increasing the complexity and improving the reliability of the devices.
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for manufacturing, testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the possibility of manufacturing a defective device. It is also helpful to be able to perform the manufacture, testing and debugging of integrated circuits in an efficient and timely manner.
To increase the number of pad sites available for a die, to reduce the electrical path to the pad sites, and to address other problems, various chip-packaging techniques have been developed. One of these techniques is controlled collapse chip connection or xe2x80x9cflip-chipxe2x80x9d packaging. With this packaging technology, bonding pads on the die include metal (solder) bumps. Electrical connection to the package is made when the die is xe2x80x9cflippedxe2x80x9d over and soldered to the package. Each bump connects to a corresponding package inner lead. The resulting packages are low profile and have low electrical resistance and a short electrical path.
Once the die is attached to such a package, the back side portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer from which an individual die is later singulated. The side of the die including the epitaxial layer and containing the transistors and other circuitry is often referred to as the circuit side, or front side of the die. The circuit side of the die is positioned very near the package and opposes the back side of the die. Between the back side and the circuit side of the die is bulk silicon. In a structural variation, a layer of insulating material is formed on one surface of a single crystal silicon wafer followed by the thin epitaxially grown silicon layer into which the transistors and other circuitry is built. This wafer structure is termed silicon on insulator (SOI). A common insulating material is silicon dioxide. When silicon dioxide is used this layer is commonly called the buried oxide layer (BOX). The transistors formed on an SOI structure show decreased drain capacitance, resulting in a faster switching transistor.
In some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage, or present new challenges. For example, when a circuit fails, or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side may be possible only from the back side of the chip. This is challenging for SOI circuits since the transistors are in a thin layer of silicon covered by the buried oxide layer and the bulk silicon. Thus, the circuit side of the flip chip die is not visible or accessible.
One technique or method for testing and analysis of circuitry in an integrated circuit includes locating defective portions of the circuitry by controlling inputs to the die and monitoring outputs in order to determine if the die is operating as designed. Defective locations may be localized in a number of ways. One method includes the use of testing circuitry located in a die, such as built-in self test (BIST) circuitry including redundant or replacement circuitry. However, concerns about maximizing use of space while minimizing manufacturing costs preclude putting extensive circuitry into a die for the sole purpose of testing. Additionally, constructing a limited number of xe2x80x9ctest dicexe2x80x9d containing testing circuitry is not effective because the test die will have a different design then the standard die and will not therefore necessarily function in the same manner.
The present invention is directed to a method for analyzing a semiconductor die using a circuit formed in a selected portion of a back side of a flip-chip die. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a semiconductor die having a buried insulator layer between a circuit side and a back side is selectively thinned. During thinning, a selected portion of a bulk silicon substrate layer on the back side is removed and a void is created. A circuit is formed in the void and is coupled to pre-existing circuitry in the circuit side of the die. The formed circuit is used to analyze or modify the performance of the die during operation and testing. The new circuitry is used in a number of implementations that assist in analyzing the die. Selectively using the formed circuitry to modify the operation of, replace, or test the pre-existing circuitry provides flexibility in die testing and operation.
In one particular example embodiment of the present invention, the circuit formed in the back side is formed over an insulator portion of silicon on insulator (SOI) structure in the die. Enough substrate is removed to expose a portion of the insulator. The circuitry includes SOI circuitry and is formed over the insulator. In one implementation, the circuitry is formed directly on the insulator portion in the die, and in another implementation additional insulator material is formed in the back side and the circuitry is formed on the additional insulator. The formed circuitry exhibits benefits including those of SOI circuitry indicated in the Background hereinabove.
In another example embodiment of the present invention, a thinning arrangement is adapted to remove a selected portion of a silicon substrate layer from a back side of an integrated circuit die. This localized thinning creates a void into which a formation arrangement is adapted to form circuitry. A coupling arrangement communicatively couples the newly formed circuitry to the pre-existing circuitry of the integrated circuit die in a manner that allows modification, replacement, or testing of the pre-existing circuitry by the newly formed circuitry. An analysis arrangement is then adapted to use the newly formed circuitry and to perform analysis of the die.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.